1. Technical Field
The present invention generally relates to a semiconductor apparatus, and more particularly, to a semiconductor apparatus which includes a resistive memory cell.
2. Related Art
A conventional DRAM includes a memory cell constituted by a capacitor, and data is stored by charging or discharging charges to and from the memory cell. However, since the capacitor has leakage current due to the characteristic thereof, the DRAM has a disadvantage in that it is a volatile memory. In order to overcome the disadvantage, memories which are nonvolatile and do not need the retention of data have been developed. In particular, attempts have been made to realize nonvolatility by modifying the structure of a memory cell. One of these attempts is a resistive memory apparatus which includes a resistive memory cell.
FIG. 1 is a view schematically showing the configuration of a conventional resistive memory apparatus. In FIG. 1, a conventional resistive memory apparatus includes a memory cell 11, first to fourth transistors N1, N2, N3, and N4, and a ground voltage Vss. The memory cell 11 is formed of a resistive substance of which resistance value changes according to a temperature or current, and has different resistance values according to the data stored therein.
The first transistor N1 supplies sensing current to sense the data stored in the memory cell 11. The first transistor N1 receives a bias voltage VB and applies a power supply voltage VPPSA to a sensing node SAI. The second transistor N2 is turned on in response to a clamping signal VCLAMP and serves to control the voltage applied to the memory cell 11 not to exceed a threshold. The third transistor N3 is turned on in response to a bit line select signal BLS and selects a bit line to which data access is to be implemented. The is fourth transistor N4 is turned on in response to a word line select signal WLS, and selects a word line to which data access is to be implemented.
The conventional resistive memory apparatus senses the data stored in the memory cell 11 by changing the voltage of the sensing node SAI. The first transistor N1 is turned when the bias voltage VB is applied, and is configured to supply a predetermined amount of current to the sensing node SAI. The current flows through the memory cell 11. Accordingly, the voltage level of the sensing node SAI changes according to the resistance value of the memory cell 11. That is to say, when the resistance value of the memory cell 11 is large, the voltage of the sensing node SAI has a high level, and when the resistance value of the memory cell 11 is small, the voltage of the sensing node SAI has a low level. In this way, in the conventional resistive memory apparatus, the predetermined amount of current is supplied to the sensing node SAI, and the data stored in the memory cell 11 is sensed through a change in the voltage level of the sensing node SAI according to the resistance value of the memory cell 11.
Further, in order to reliably sense a change in the voltage level of the sensing node SAI according to the resistance value of the memory cell 11, a boosting voltage VPPSA is used as the power supply voltage. In general, the boosting voltage VPPSA may be generated to a voltage with a level higher than the level of an external voltage, through a pumping circuit.